Table 1 Advantages and challenges of SOI wafer fabrication method

SIMOX

Precision in controlling BOX layer

Cost and defect management

Simplicity of the process

Lattice defect of device layer

Localized BOX layer formation in wafer

Oxide precipitates in device layer and silicon pipe in BOX layer

Smart Cut™

Precision in controlling device layer

Limitations in defect-free SOI wafer

Uniform device layer and BOX layer from nm to \(\upmu\)m

Increased process complexity and cost due to the multiple process steps

Reuse of high-quality seed wafers

Requirement of high bonding quality

Ability to change the materials of the device layer and handle layer

Eltran\(^\circledR\)

Absence of COP occurrence in the device layer

Reflection of the porous silicon roughness

High quality device layer due to absence of ion implantation

Occurrence of stacking faults in epitaxy process

Device layer and BOX layer from nm to \(\upmu\)m

High cost and low yield due to multiple process steps and inherent complexity

BSOI/BESOI

Device layer with a thickness more than 10 \(\upmu\)m

Material wastage due to thinning down

Lower defect density

Damage during the mechanical grinding process