Fig. 3

a 3D schematic illustrating the fabrication of SOI wafers through the Eltran\(^\circledR\) technology. b Cross-sectional images of double layered porous Si formed by changing an anodic current. Reprinted from [46] with permission from Springer Nature. 3D schematic illustrating the fabrication of SOI wafers through the c BSOI and d BESOI technology. e Cross-sectional SEM images of the (top) as-etched BESOI and (bottom) the H\(_{2}\) annealed BESOI The annealing condition is 1150 \(^{\circ }\)C, 80 torr, 1 h in H\(_{2}\). Reprinted from [47] with permission from AIP Publishing