Fig. 2

a 3D schematic illustrating the fabrication of SOI wafers through the SIMOX technology. b Cross-sectional TEM images of (left) the as-implanted sample and (right) the annealed high-quality low-dose SIMOX with a 60 nm-thick buried oxide layer. Reprinted from [9] with permission from Springer Nature. c Cross-sectional TEM image of both conventional low-dose SIMOX and ITOX SIMOX wafers following the removal of the surface oxide layer. Reprinted from [10] with permission from Springer Nature. d Cross-sectional XTEM image of the annealed wafer partially subjected to an oxygen ions. Reprinted from [11] with permission from Elsevier. e 3D schematic illustrating the fabrication of SOI wafers through the Smart Cut™ technology. f Cross-sectional TEM image of the implanted zone. Reprinted from [12] with permission from Elsevier. g Cross-sectional TEM image of a 100 mm InP-on-silicon substrate after \(\sim\)0.5 \(\upmu\)m InP film overgrowth by MOCVD. Reprinted from [13] with permission from John Wiley and Sons