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Table 3 Published work comparison regarding voltage multiplier

From: RF power harvesting: a review on designing methodologies and applications

Ref. Rectifier topology No. of stage Freq. (MHz) Tech. Range (dBm) Maximum PCE Size
[51] Differential 2 433 0.18 µm CMOS 0–20 74% @ 2 dBm
[52] PMOS transistors 7 900 40 nm CMOS 44% @ > 390 mV 0.04 mm2
[53] Half-wave 4 900 0.18 µm CMOS 37.42% @ 390 mV
[54] Comparator-based/active-diode 3 13.56 0.18 µm CMOS 8–15 67.9% @ 12.8 dBm
[55] Dickson 3 13.56 250 nm CMOS 72% 0.13 mm2
[56] 915 0.13 µm CMOS −21.6 22.6% @ −16.8 dBm 0.186 mm2
[57] 900, 2400 130 nm CMOS 41% @ −20.6 dBm